1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device.
2. Description of the Related Art
As refinement technologies are pushed to the limit for improving the bit density of non-volatile semiconductor storage devices such as NAND type flash memory, there is increasing demand for lamination of memory cells. As one example, there have been proposed lamination-type non-volatile semiconductor storage devices where memory cells are configured with vertical transistors (see, for example, Japanese Patent Laid-Open No. 2007-266143). The lamination-type non-volatile semiconductor storage device comprises a plurality of memory blocks that are configured in erase units. Each memory block has memory strings, each of which has a plurality of memory cells connected in series. Each memory string has a columnar semiconductor layer, a MONOS layer formed to surround the columnar semiconductor layer, and a conductive layer formed to surround the MONOS layer.
Conventionally, in the above-mentioned non-volatile semiconductor storage device, the erase operation is performed per memory cell block. That is, in the erase operation, all data is first erased from each memory block, and any data that does not need to be erased is written back to the memory block. As such, this erase operation requires write-back of data, which can be time-consuming.